The present invention relates to a single chip microcomputer internally including a flash memory.
A single chip microcomputer internally including a microprocessor and a flash memory both formed on a single chip (called simply a xe2x80x9csingle chip microcomputerxe2x80x9d hereinafter) is used at present. Now, a prior art single chip microcomputer will be described with reference to FIG. 1. The shown single chip microcomputer, generally designated by the reference number 1, internally includes a flash memory 2, a communication port 5, a CPU. (central processing unit) 4, an internal ROM (read only memory) 3, and a programming control circuit 6, which are coupled through an internal bus as shown in FIG. 1.
The flash memory 2 includes an internal area, which is divided into arbitrary areas (A or B), which are managed independently of each other, so that a writing, a reading and a flash erasing can be carried out in units of one divided area.
The communication port 5 is connected to an external write device (not shown) which is external of the flash memory 2, for transferring various information including a write data and a dedicated command between the flash memory 2 and the external device.
The CPU 4 manages the whole of the single chip microcomputer 1, and executes a processing based on a program included in the internal ROM 3 or the flash memory 2.
The internal ROM 3 previously stores a communication algorithm 9 which describes the procedure for transferring information through the communication port 5, and a programming algorithm 8 which describes the procedure for performing the writing and the erasing to an arbitrary area in the flash memory 2.
The programming control circuit 6 is controlled by the CPU 4 to execute the actual writing, reading and erasing to the flash memory 2.
In the single chip microcomputer 1, if a dedicated command is inputted from the write device in an operation mode dedicated for the programming, the CPU 4 controls the programming control circuit 6 in accordance with the procedure described in the programming algorithm 8, so that the writing, the reading or the flash erasing is executed for the arbitrary area in the flash memory 2.
As mentioned above, in the prior art single chip microcomputer 1, the programmed operation such as the writing the reading and the erasing for an arbitrary area in the flash memory 2. is unlimitedly executed by the dedicated command. Therefore, the write device has all authority for executing the programmed operation. In other words, no security for information in the flash memory 2 is considered. Therefore, a program already stored in the internal flash memory can be analyzed or modified by an unauthorized person, and accordingly, a copy right of software cannot be protected.
Japanese Patent Application Pre-examination Publication No. JP-A-04-017477 (an English abstract of JP-A-04-017477 is available and the content of the English abstract of JP-A-04-017477 is incorporated by reference in its entirety into this application) proposes a technology for controlling a so-called IC card or smart cart. FIG. 2 is a block diagram showing the construction of the 1C disclosed in JP-A-04-017477.
The IC card, generally designated by the reference number 20, includes a microcomputer 21, which comprises an internal memory 25. This internal memory 25 is previously written with a basic processing program such as a communication program to communicate within terminal device 28 and an external memory 22 through a bus, a check program for checking whether or not information is correct when the communication is performed, and a secret protecting program including a pass word. Furthermore, the microcomputer 21 includes a CPU for executing a necessary processing in accordance with a program stored in the internal memory 25 or the like, and an interface 23.
The external memory 22 provided in parallel to the microcomputer 22, is constituted of a PROM (programmable ROM), and includes a user program area 26 which can be freely written by a program used for a processing required by a user. and a data area 27 which can be written with necessary data.
The internal memory 25 is previously written with an address of the user program 26 in the external memory 22, and a heading address and an ending address of the data area 27. Therefore, when the loading of the user program is completed, the ending address of the user program area 26 is written with a mark which indicates the completion of the writing of the user program.
Therefore, inhibition of a re-loading of the user program to the user program area 26 is checked on the basis of whether or not there exists the mark which indicates the completion of the writing of the user program. On the other hand, inhibition of writing and reading to the data area 27 is realized by preparing a pass word function, a code checking, and encryption, in the user program area 26, in the form of a program.
However, JP-A-04-017477 merely describes a general IPL (initial program loader) function, which is already practiced in an early personal computer. But, JP-A-04-017477 does not disclose a data handling manner and a processing means, for security necessary for protecting the copy right.
When the external memory 22 is constituted of an EEPROM (electrically erasable PROM), it becomes possible to erase in units of a block. However, the above mentioned microcomputer does not describe an electrically erasing at all.
Accordingly, it is an object of the present invention to provide a single chip microcomputer which has overcome the above mentioned problems of the prior art.
Another object of the present invention is to provide a single chip microcomputer capable of easily managing the writing, reading and erasing to the flash memory provided with a security means, and on the other hand, having a security of the degree sufficient to protect the copy right.
The above and other objects of the present invention are achieved in accordance with the present invention by a single chip microcomputer internally including a microprocessor and a flash memory both formed on a single chip, wherein the flash memory includes a first area, and a second area for designating whether or not it is permissible to program the first area, and wherein when the microprocessor receives a programming request from an external device, the microprocessor refers to the second area to determine whether or not a programming of the first area should be executed.
With the above mentioned arrangement, by referring to a write inhibition flag, a read inhibition flag and an erase inhibition flag, which are management information for managing the first area , it is possible to easily perform a management of the first area in the flash memory, such as permission and inhibition of the writing, reading and erasing to the flash memory.
In one embodiment of the single chip microcomputer, when the microprocessor has executed the programming of the first area, the microprocessor writes an instruction of inhibiting the programming of the first area, into the second area.
With this arrangement, from the view point of protecting the copy right of a software and of ensuring a security of the system, it is possible to voluntarily inhibit an intentional programming (including the writing, reading and erasing) to the flash memory.
Preferably, the single chip microcomputer further internally includes a read only memory which stores a programming algorithm for determining whether or not execution of the programming is permissible, and the microprocessor is controlled in accordance with the algorithm stored in the read only memory to refer to the second area.
Alternatively, the single chip microcomputer further internally includes a read only memory which stores a loader program for loading a programming algorithm for determining whether or not execution of the programming is permissible, from an external device to an internal memory, and the microprocessor is controlled in accordance with the programming algorithm stored in the internal memory to refer to the second area.